7 Series GTX/GTH/GTP TX Buffer bypass ports TXSYNCMODE, TXSYNCALLIN & TXSYNCIN are documented as "Reserved. Tie to 1'b0" in UG476 v1.9.1 and UG482 v1.5. However, 7 Series FPGAs Transceivers Wizard v2.6 or earlier does not set these ports to 1'b0. Can this wrong setting cause any issue?
TXSYNCMODE, TXSYNCALLIN and TXSYNCIN input ports are for only buffer bypass auto mode. For the buffer bypass manual mode, these ports are "Don't Care." Users can ignore the Wizard setting of these ports when using buffer bypass manual mode.