If configuring an Stacked Silicon Interconnect Technology (SSIT) device over JTAG, my design does not start up as expected.
Can JTAG configurarion affect how my deisgn will initialize?
Delay between the startup of SLRs in an SSIT device can be seen after JTAG configuration. This will occur if the configuration startup clock is not set to JtagClk. For non-SSIT devices iMPACT the startup clock setting should have no affect on device initialization. However, for SSIT devices, the startup clock must be set to JTAG. The algorithm iMPACT uses will not start up all SLR at once unless JTAG clock is selected at bitstream generation. To do this:
set_property BITSTREAM.STARTUP.STARTUPCLK JtagClk [current_design]