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AR# 56156

Zynq-7000 SoC, PS PLLs – What is the jitter on the FCLK when using the PLLs that reside in the PS?


How much jitter is generated on the FCLK outputs?


The Processing System 7 block will derate the Zynq-7000 PL FCLK rate by 3% to include all jitter sources in the PS.

The following clock constraints are added to the Processing System 7 .xdc file upon generation of the output products:

create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.6
set_clock_groups -asynchronous -group {clk_fpga_0}

There are currently no plans to provide more specific representations of FCLK jitter.
AR# 56156
Date 05/17/2018
Status Active
Type General Article
  • Zynq-7000
  • ISE Design Suite - 14.5
  • Vivado Design Suite - 2013.1
  • ISE Design Suite - 14.6
  • ISE Design Suite - 14.7
Boards & Kits
  • Zynq-7000 SoC Boards and Kits
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