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AR# 56170

AXI Bridge for PCI Express v1.07.a - Incorrect NCF and UCF period constraint generated when using 100 MHz or 250 MHz reference clock

Description

Version Found: v1.07a
Version Resolved and other Known Issues: See (Xilinx Answer 44969).

When using the AXI PCIe IP with a 100 MHz or 250 MHz reference clock, the AXI PCIe IP must be configured with Clock Frequency of REFCLK Input set to 0 or 2 respectively. However, this creates an incorrect NCF/UCF constraint as shown below:

It is declared as:

TIMESPEC TSidentifier =PERIOD period

Whereas, it should be:

TIMESPEC TSidentifier =PERIOD TNM_reference period.

The following constraints are generated in the NC/UCF:

TIMESPEC "TS_SYSCLK" = PERIOD 100.00 MHz HIGH 50 %; for REFCLK input set to 0
TIMESPEC "TS_SYSCLK" = PERIOD 250.00 MHz HIGH 50 %; for REFCLK input set to 2

Whereas it should be:

TIMESPEC "TS_SYSCLK" = PERIOD My_TNM_reference 100.00 MHz HIGH 50 %; for REFCLK input set to 0
TIMESPEC "TS_SYSCLK" = PERIOD My_TNM_reference 250.00 MHz HIGH 50 %; for REFCLK input set to 2

How can I fix this problem?

Solution

To work around this issue, open the TCL file for the AXI PCIe IP in the EDK install directory:

<XILINX_EDK>\hw\XilinxProcessorIPLib\pcores\axi_pcie_v1_05_a\data\axi_pcie_v2_1_0.tcl

Change line 514 as follows:

From:

puts $outputFile "TIMESPEC \"TS_SYSCLK\" = PERIOD 100.00 MHz HIGH 50 %;"

To:

puts $outputFile "TIMESPEC \"TS_SYSCLK\" = PERIOD \"SYSCLK\" 100 MHz HIGH 50 %;"

Change line 523 as follows:

From:

puts $outputFile "TIMESPEC \"TS_SYSCLK\" = PERIOD 250.00 MHz HIGH 50 %;"

To:

puts $outputFile "TIMESPEC \"TS_SYSCLK\" = PERIOD \"SYSCLK\" 250 MHz HIGH 50 %;"

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/29/2013 - Initial release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
53114 AXI Bridge for PCI Express v1.05.a - Incorrect UCF constraint generated when using 250 MHz reference clock N/A N/A
AR# 56170
Date Created 05/29/2013
Last Updated 05/30/2013
Status Active
Type General Article
Devices
  • Kintex-7
Tools
  • EDK - 14
  • PlanAhead - 14
IP
  • 7 Series Integrated Block for PCI Express (PCIe)