Table 2-7 of (UG472) states that the CE and CLR ports of a BUFR "cannot be used in BYPASS mode".
However, if I comment out the CE and CLR inputs in a VHDL design, I receive the following error:
How should this be handled?
What the Clocking Resources Guide is trying to explain in table 2-7 is that these inputs (CE and CLR) should not be connected to signals that change.
If you do connect them to a signal you will receive the following Map warning which lets you know that these will not be used even though you have connected them:
The CE and CLR pins should be tied '1' and '0' respectively to avoid both the synthesis error and the Map warning.