We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56211

Does Vivado Synthesis support two dimensional array initialization using reg declaration?


The following statement occurs in a System Verilog HDL file.

reg [7:0] mem [2:0] = '{8'haa, 8'h55,8'h99};

Upon synthesizing the above line of code with Vivado Synthesis and running post-synthesis simulation, I observe that the 0th element of the array is assigned to 8'haa and the remaining elements being assigned to 0 which is incorrect.

How do I resolve this issue?


Two-dimensional register initialization is not supported by Vivado Synthesis.

To work around this issue, use either of the following solutions.

1. Assign individual elements of array as follows:

assign mem[0] = {8'h99};
assign mem[1] = {8'h55};
assign mem[2] = {8'haa};

2. Initialize the memory using a readmemh/readmemb statement.

AR# 56211
Date Created 06/03/2013
Last Updated 04/16/2014
Status Active
Type Known Issues
  • Vivado Design Suite