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AR# 56212

ISE Design Suite 14.6 MAP - False LIT error occurs when IOBDELAY property is combined with loadless net

Description

A false Logical DRC error can be printed when a PAD symbol has an IOBDELAY=NONE property and the input path has all of its loads trimmed, so it is loadless.

This is an issue in the connectivity checking for Logical DRC.

ERROR:LIT:536 - IBUF symbol "dio66_IOBUF/IBUF" (output signal=N859) has the attribute IOBDELAY set to value NONE and it is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it has precedence over the IBUF one. Either the constraint or the design need modification to prevent an unroutable situation.

Solution

This error can be avoided in several ways:

  • Remove the IOBDELAY=NONE property from the pad.
  • Ensure that the input path has valid loads or disable the trimming (map -u).
  • Set the following environment variable to bypass the failing check:

    Linux:
    setenv XIL_MAP_NO_IOBDELAY_IODELAY_DRC 1

    Windows:
    SET XIL_MAP_NO_IOBDELAY_IODELAY_DRC=1


For general information about setting ISE software environment variables, see (Xilinx Answer 11630).

 

This issue has been fixed in ISE Design Suite 14.7.

AR# 56212
Date Created 06/03/2013
Last Updated 03/02/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite - 14