We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56225

2013.2 fir_compiler_v7_1 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output


FIR compiler v7.1 fails in simulation with a M_AXIS_DATA_TDATA mismatch error with the following configuration:

Filter Type = Interpolation

Channel Sequence = Advanced

Optimization Goal = Speed OR
Optimization Goal = Custom and Optimization List contains Control_LUT_Pipeline

Has ARESETn = true

When you apply a reset, then the output sample values might mismatch between the behavioral model and the post synthesis/implementation simulation models for the first N samples; where N = Number of Channels * Interpolation Rate. After the first N samples, the model outputs will then match. The mismatch only occurs for a specific timing relationship between the qualified input samples; s_axis_data_tvalid and aresetn.


This is a known issue with FIR Compiler v7.1 using the configuration above.

To work around this issue, perform one of the following work-arounds:

Work-around 1:

Assert aresetn for 3 clock cycles rather than the minimum requirement of 2 clock cycles.

Work-around 2:

Deselect the Control_LUT_Pipeline optimization.

AR# 56225
Date Created 06/04/2013
Last Updated 09/18/2013
Status Active
Type Known Issues
  • FIR Compiler