We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56231

MIG 7 Series DDR3/2 - In some instances, the MIG default pin-out will assign an empty address/ctrl byte group


Version Found: MIG 7 Series v1.6
Version Resolved: See (Xilinx Answer 54025)

In some configurations, MIG 7 Series assigns an Address/Ctrl group to a byte lane with no signals in it. 

For example, MIG 7 Series may assign Address/Ctrl 0-2 and DQ[0-7] in one bank, and then DQ[8-15] in another where Address/Ctrl0 has no signals. 

In this case, an interface that should fit into one bank gets split into two.  

MIG should never assign a byte group with no signals.  

This will be resolved in a future release.  Please see the following manual work around.


This can be manually worked around by unassigning the empty byte group. 

In the example above, Address/Ctrl-0 can be unassigned and then the second data byte can be moved into that bank to contain the interface in a single bank. 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56231
Date Created 06/04/2013
Last Updated 04/15/2014
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series