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AR# 56245

LogiCORE IP LTE RACH Detector v2.0 - Simulation failure occurs in the Vivado 2013.1 post-synthesis Verilog model


The simulation failure occurs in the Vivado post-synthesis Verilog model. 

The failure can occur in any RACH configuration which uses multiple frequency channels where the Number of Frequency Channels is greater than 5.

The error manifests as an incorrect output on the RACH channel. 

The cause of the error is incorrect RAM initialization in the frequency demodulator. 

This demodulates the RACH signal incorrectly, creating a failed correlation result.


A suitable workaround is to simulate using either:

  • The post-synthesis VHDL model.
  • The post-implementation Verilog.

For the LogiCORE IP LTE RACH Detector - Release Notes and Known Issues, see (Xilinx Answer 54487).

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Master Answer Records

AR# 56245
Date Created 06/05/2013
Last Updated 08/20/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.1
  • 3GPP LTE RACH Detector