We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5630

V1.5.2 CORE Generator - Information on the v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (SP 1 and 2 for Foundation F1.5i or Alliance A1.5i).


Keywords: CORE Generator, COREGen, patch, service pack, 1, 2, a1.5i, f1.5i, foundation,

Urgency: Standard

General Description:
This solution contains information regarding the CORE Generator v1.5.2 shipped
with Foundation and Alliance 1_5i Service Packs 1 and 2.


The CORE Generator v1.5.2 update is packaged as follows with the following M1_5i
Service Pack 1 updates:

- Foundation 1_5i Service Pack 1: coregen_upd.exe

- Alliance 1_5i Service Pack 1 for PC's: 15i_sp1_cgen_ws.tar.gz

- Alliance 1_5i Service Pack 1 for Workstations: 15i_sp1_cgen_ws.tar.gz

REQUIREMENTS: The CORE Generatorn updates in the 1_5i Service Packs above
are incremental updates and must be installed over existing v1.5.0 installations.

Please note that these updates are SOFTWARE-ONLY. New COREs are available on the Xilinx CoreLINX web page at:



CR 108040:
"Warning 9199: Unknown component - B998, TBUF" when loading design
containing COREGen Sine-Cosine LUT, FIFO, ROM, or RAM components into
the F1.5 Foundation simulator.

(Xilinx Solution 4521)

CR 106196:
Pin mismatch".
COREGEN does not allow you to select the netlist bus delimiter format if one of
your selections is VHDL or Verilog Instantiation Template.

(Xilinx Solution 4041)

In addition, a number of datasheets have been updated in this incremental
update, including:

- Synchronous FIFO - improved timing diagram)
- SDA FIR Filter - added description of calculation of output bit width
- PDA FIR Filter - (CR 107205, 4KXL-08 speed data, description of c_m_o[n:0]
and c_d_o[n:0] output pins,
- Dual Port Block RAM - added description of MIF files required for initialization
of Virtex block RAM in HDL behavioral simulation
(Xilinx Solution 5218)
AR# 5630
Date Created 08/31/2007
Last Updated 02/15/2001
Status Archive