In a simple IP Integrator design where the AXI bus is made external, with the protocol changed from AXI4 to AXI4LITE in the CONFIG settings for the port, the HDL wrapper still produces AXI4 signals and not the reduced signals expected for AXI4LITE.How can I address this?
First, remove the HDL wrapper. Then, in sources view, right click on the block design and Generate Output Products.
Next, close the Block design and relaunch. Finally, Re-generate the HDL wrapper and the signals should now be correct.