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AR# 56329

JESD204B - How to share TX and RX lanes of a core when the lanes do not match

Description

PG066 mentions that the JESD204 core can share TX/RX lanes within a Transceiver, even if they do not match.

How is this done?

Solution

This requested setup can be created as follows:
 
  1. Generate a 4-lane shared JESD204 core.
  2. In the block level, comment out the Rx JESD204 instantiation.
  3. Instantiate two Rx JESD204 cores. This can be done by copying the existing Rx instantiation that was created by the core (see code below).
  4. Each JESD204 core has a parameter called .C_LANES.  In the two instantiated Rx cores, set this value to 2.
  5. Change some of the inputs and outputs of the core to match the two instantiations below. (For steps 3-5 copy code below)
 
      //First Rx JESD204 core
      jesd204_v4_0_top #(
          .C_ELABORATION_TRANSIENT_DIR (C_ELABORATION_TRANSIENT_DIR),
          .C_COMPONENT_NAME            (C_COMPONENT_NAME),
          .C_FAMILY                    (C_FAMILY),
          .C_NODE_IS_TRANSMIT          (0),
          .C_LANES                     (2),
          .C_USE_BRAM                  (C_USE_BRAM),
          .C_LMFC_BUFFER_SIZE          (C_LMFC_BUFFER_SIZE),
          .C_DEVICE_SUBCLASS           (C_DEVICE_SUBCLASS)
          )
        i_jesd204_0_rx_0 (
         // Clk and Reset
          .clk                     (rx_core_clk),
          .rst                     (rx_core_rst),
 
          // Common
          .support_lane_sync       (rx_cfg_support_lane_sync),
          .lanes_in_use            (rx_cfg_lanes_in_use),
          .test_modes              (rx_cfg_test_modes),
 
          .start_of_frame          (rx_start_of_frame),
          .start_of_multiframe     (),
          .end_of_frame            (rx_end_of_frame),
 
          .sysref_always           (rx_cfg_sysref_always),
          .sysref_in               (rx_sysref_r),
          .sysref_out              (),
 
          // Rx
          .octets_per_frame        (rx_cfg_octets_per_frame),
          .scram_enable            (rx_cfg_scram_enable),
          .frames_per_multiframe   (rx_cfg_frames_per_multi),
          .rx_buffer_delay         (rx_cfg_buffer_delay),
          .rx_buffer_adjust        (rx_buffer_adjust[19:0]),
          .disable_error_reporting (rx_cfg_disable_error_reporting),
          .init0                   (rx_init0[63:0]),
          .init1                   (rx_init1[63:0]),
          .init2                   (rx_init2[63:0]),
          .init3                   (rx_init3[63:0]),
          .test_err_count          (rx_test_err_count[63:0]),
          .test_ila_count          (rx_test_ila_count[63:0]),
          .test_mf_count           (rx_test_mf_count[63:0]),
 
          .rxdata                  (rxdata[63:0]),
          .rxcharisk               (rxcharisk[7:0]),
         .rxdisperr               (rxdisperr[7:0]),
          .rxnotintable            (rxnotintable[7:0]),
 
          .rx_sync                 (rx_sync_i_1),
          .encommaalign            (rxencommaalign),
 
          .rxdataout               (rxdataout[63:0]),
          .frame_error             (rx_frame_error[7:0]),
 
          // Tx ports (unused)
          .multi_frames            (8'b0),
          .tx_cfg_f                (8'b0),
          .tx_cfg_k                (5'b0),
          .tx_cfg_scr              (1'b0),
          .tx_cfg_did              (8'b0),
          .tx_cfg_bid              (4'b0),
          .tx_cfg_m                (8'b0),
          .tx_cfg_cs               (2'b0),
          .tx_cfg_n                (5'b0),
          .tx_cfg_np               (5'b0),
          .tx_cfg_s                (5'b0),
          .tx_cfg_hd               (1'b0),
          .tx_cfg_res1             (8'b0),
          .tx_cfg_res2             (8'b0),
          .tx_cfg_cf               (5'b0),
          .tx_cfg_adjcnt           (4'b0),
          .tx_cfg_adjdir           (1'b0),
          .tx_cfg_phadj            (1'b0),
          .tx_cfg_cs_all           (1'b0),
 
          .tx_sync                 (1'b0),
 
          .txdatain                (64'b0),
 
          .txdata                  (),
          .txcharisk               ()
        );
 
      //Second Rx JESD204 core
         jesd204_v4_0_top #(
          .C_ELABORATION_TRANSIENT_DIR (C_ELABORATION_TRANSIENT_DIR),
          .C_COMPONENT_NAME            (C_COMPONENT_NAME),
          .C_FAMILY                    (C_FAMILY),
          .C_NODE_IS_TRANSMIT          (0),
          .C_LANES                     (2),
          .C_USE_BRAM                  (C_USE_BRAM),
          .C_LMFC_BUFFER_SIZE          (C_LMFC_BUFFER_SIZE),
          .C_DEVICE_SUBCLASS           (C_DEVICE_SUBCLASS)
          )
        i_jesd204_rx_1 (
          // Clk and Reset
          .clk                     (rx_core_clk),
          .rst                     (rx_core_rst),
 
          // Common
          .support_lane_sync       (rx_cfg_support_lane_sync),
          .lanes_in_use            (rx_cfg_lanes_in_use),
          .test_modes              (rx_cfg_test_modes),
 
          .start_of_frame          (rx_start_of_frame2),
          .start_of_multiframe     (),
          .end_of_frame            (end_of_frame2),
 
          .sysref_always           (rx_cfg_sysref_always),
          .sysref_in               (rx_sysref_r),
          .sysref_out              (),
 
          // Rx
          .octets_per_frame        (rx_cfg_octets_per_frame),
          .scram_enable            (rx_cfg_scram_enable),
          .frames_per_multiframe   (rx_cfg_frames_per_multi),
          .rx_buffer_delay         (rx_cfg_buffer_delay),
          .rx_buffer_adjust        (rx_buffer_adjust[39:20]),
          .disable_error_reporting (rx_cfg_disable_error_reporting),
          .init0                   (rx_init0[127:64]),
          .init1                   (rx_init1[127:64]),
          .init2                   (rx_init2[127:64]),
          .init3                   (rx_init3[127:64]),
          .test_err_count          (rx_test_err_count[127:64]),
          .test_ila_count          (rx_test_ila_count[127:64]),
          .test_mf_count           (rx_test_mf_count[127:64]),
 
          .rxdata                  (rxdata[127:64]),
          .rxcharisk               (rxcharisk[15:8]),
          .rxdisperr               (rxdisperr[15:8]),
          .rxnotintable            (rxnotintable[15:8]),
 
          .rx_sync                 (rx_sync_i_2),
          .encommaalign            (rxencommaalign),
 
          .rxdataout               (rxdataout[127:64]),
          .frame_error             (rx_frame_error[15:8]),
 
          // Tx ports (unused)
          .multi_frames            (8'b0),
          .tx_cfg_f                (8'b0),
          .tx_cfg_k                (5'b0),
          .tx_cfg_scr              (1'b0),
          .tx_cfg_did              (8'b0),
          .tx_cfg_bid              (4'b0),
          .tx_cfg_m                (8'b0),
          .tx_cfg_cs               (2'b0),
          .tx_cfg_n                (5'b0),
          .tx_cfg_np               (5'b0),
          .tx_cfg_s                (5'b0),
          .tx_cfg_hd               (1'b0),
          .tx_cfg_res1             (8'b0),
          .tx_cfg_res2             (8'b0),
          .tx_cfg_cf               (5'b0),
          .tx_cfg_adjcnt           (4'b0),
          .tx_cfg_adjdir           (1'b0),
          .tx_cfg_phadj            (1'b0),
          .tx_cfg_cs_all           (1'b0),
 
          .tx_sync                 (1'b0),
 
          .txdatain                (64'b0),
 
          .txdata                  (),
          .txcharisk               ()
        );
 
6. Create the following wires:
 
wire [3:0]   rx_sync_i_1; 
wire [3:0]   rx_sync_i_2; 
wire rx_sync1;   
wire rx_sync2; 
wire [3:0]   rx_start_of_frame2;                         
wire [3:0]   rx_end_of_frame2;
7. Locate the following lines of code: 
 
           // Combine together the 4 rx_sync_i bits.
           assign rx_sync = &rx_sync_i;
 
Change this to:
 
        assign rx_sync1 = &rx_sync_i_1; //sync output from first rx jesd204 core
        assign rx_sync2 = &rx_sync_i_2; //sync output from second rx jesd204 core
        assign rx_sync = rx_sync1 & rx_sync2;
This takes the two sync outputs from each Rx core and combines them into one.
 
8. Locate the following piece of code
 
      // Capture and hold the very first start_of_frame for all lanes.
      always @(posedge rx_core_clk)
         if (rx_core_rst | !rx_sync)
            rx_start_of_frame_hold <= 1'b0;
          else if (rx_start_of_frame != 4'b0000)
             rx_start_of_frame_hold <= 1'b1;
Change this to:
 
        always @(posedge rx_core_clk)
         if (rx_core_rst | !rx_sync)
            rx_start_of_frame_hold <= 1'b0;
          else if (rx_start_of_frame != 4'b0000 && rx_start_of_frame2 != 4'b0000)
            rx_start_of_frame_hold <= 1'b1;
 
9. If required, rx_start_of_frame2 and rx_end_of_frame2 can be made outputs just like rx_start_of_frame and  rx_end_of_frame. 

Remove them as wires and set them as outputs.
AR# 56329
Date Created 06/11/2013
Last Updated 10/21/2014
Status Active
Type General Article
IP
  • JESD204