In Vivado 2013.1, BRAM optimizations have been enabled by default in the opt_design step.
Users can expect to see an average of 40% power saving for BRAMs through clock gating algorithms.
In addition, BRAMs that satisfy certain WRITE_MODE and ENABLE conditions can save additional power through optimizations.
This power saving is reflected in the BRAM component of the Core Dynamic power in XPE 2013.1.
This ensures that Vivado and XPE correlate better in their estimates.
The 40% BRAM power savings figure comes from extensive benchmarking conducted by Xilinx R&D on a large suite of customer designs we have in-house.
This number is an average with some designs showing more savings while others show lower savings.
Overall, we recommend that customers use Vivado power estimation with an SAIF activity file (that models the real world operation of the FPGA) to get the best correlation with hardware measurements.
To disable the BRAM power_opt, please see (Xilinx Answer 56747)