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AR# 56363

Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured

Description

The Design Advisory covers the Spartan-6 family. When boundary scan testing is carried out on a configured Spartan-6 device, incorrect values can be driven by EXTEST and read on the SAMPLE instructions. When the IOB is configured to include an inverter, this inverter is included on the path from the pad to the Boundary Scan cell. This will result in unexpected values being driven and/or sampled by the cell and subsequent failures of the boundary scan test vector. The SAMPLE, PRELOAD, EXTEST, INTEST JTAG instructions can all be affected. This will only occur when the device is configured and only if the IOB is configured to include an inverter.

Solution

The following conditions will cause this issue to occur during BSCAN testing on a pin:

  • Spartan-6 FPGA is configured
  • An IOB is programmed to include an inverter

There are a number of work-arounds that can be employed.

(1) Prevent FPGA configuration. This can be achieved by holding the INIT pin Low, or alternatively changing the MODE pin values if configuring from flash.
(2) Clear prior configuration using PROG pin or a power cycle and prevent re-configuration.
(3) Overwrite the FPGA configuration with a design that does not use inversion at the inputs. This can be done on a JTAG tool using an SVF file. A dummy design with some simple logic can be created and generated using compression in BitGen. This will minimize the SVF load time.
(4) Modify the original design to avoid the IOB invert path. You could identify the IOBs that use the invert path (e.g., via FPGA Editor or via inverted boundary scan values) and place the inverter in a CLB. See below for an instance of a LUT1 inverter that is placed in CLB using a UCF LOC constraint.

VHDL:

  -- LUT1 inverter
  LUT1_inst : LUT1
    generic map (INIT => "01")
    port map (
      O => LED7, -- LUT general output
      I0 => IN7 -- LUT input
    );

UCF:

  # UCF Constraint places LUT1_inst inverter into a SLICE (versus into the IOB)
  INST LUT1_inst LOC=SLICE_X*Y*;

Revision History
6/13/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
AR# 56363
Date Created 06/12/2013
Last Updated 02/18/2014
Status Active
Type Design Advisory
Devices
  • Spartan-6
Tools
  • ISE Design Suite