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AR# 56365

Virtex-5 GTX - ISE 14.x - The line rate I selected in the IBERT CORE Generator GUI is not the line rate I see in the IBERT Analyzer


When generating a ChipScope IBERT design for a Virtex-5 in ISE 14.x, the line rate displayed in the ChipScope IBERT analyzer window may not be what was selected in the ChipScope IBERT CORE Generator. This is a known issue and only affects the line rate that is being displayed in the GUI. This does not affect the actual rate that is running on the hardware. The rate that is running on the hardware is the rate that was selected when generating the core.


The issue is how the selected system clock frequency is being passed to the CORE Generator. It is not being encoded properly, and due to this the IBERT core expects a different system clock than what was selected in the CORE Generator GUI. Again, this does not affect the actual line running to the hardware, it only effects what is being displayed by the GUI.
To verify that the hardware is running the correct line rate, the following equation can be used. Below is an example:

Example .XCO
CSET sysclock_frequency=100
CSET sysclock_mode=external_clock
CSET sysclock_pin_ip_std=LVCMOS25

This states that we want an external 100 MHz system clock.
If we look at the chipscope_ibert_top.ucf, (in chipscope_ibert/example_design folder) I see this:

# Sysclk Timing Constraints
# External Clock Source

This tells us that the sysclk frequency encoded in the core is wrong, and it is 156.25.

This equation below can be used to correlate the line rate seen in the IBERT Analyzer GUI to the actual line rate running on the hardware.

Actual line rate = reported line rate in GUI * (correct sysclk freq / UCF sysclk frequency)
Actual line rate = 4.688 * (100 / 156.25 ) = 3.000

4.688 is the line rate being displayed in the IBERT Analyzer GUI
100 is the system clock frequency I entered into the ChipScope CORE Generator GUI
156.25 is the system clock frequency that is in the UCF file (actual system clock frequency expected)
3.000 is the line rate I expected to be running in the hardware, and is the expected value that should be displayed in the IBERT analyzer GUI.

Also note that if I had supplied the core with a 156.25 (expected sysclk frequency), I would see 3.000 as the correct line rate in the IBERT analyzer GUI.

AR# 56365
Date Created 06/12/2013
Last Updated 06/18/2013
Status Active
Type General Article
  • Virtex-5
  • ISE
  • ChipScope Pro IBERT for Virtex-5 GTX