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AR# 56376

LogiCORE DUC/DDC Compiler v3.0 - Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation

Description

Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation. The output of the core, SREG_PRDATA, will be all-X.

Solution

This is a known issue with DUC/DDC Compiler v3.0.

A workaround is to use Mentor Graphics ModelSim or QuestaSim as the simulator for behavioral simulation. This may be configured in the Vivado GUI project options dialog.

For a detailed list of LogiCORE IP DUC/DDC Compiler Release Notes and Known Issues, see (Xilinx Answer 54476).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54476 LogiCORE IP DUC/DDC Compiler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56376
Date Created 06/12/2013
Last Updated 06/26/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.2
IP
  • DUC/DDC Compiler