My System Generator model has a shared memory. When I export the EDK Pcore with dual clocks for the model, it sets WRITE_MODE to READ_FIRST for the shared memory port on the EDK side.
According to the Answer Record 34859, this may corrupt the block RAM under certain conditions. See (Xilinx Answer 34859)
This is a known issue and has been fixed in System Generator 14.6 by setting the "c_write_mode_b" to "WRITE_FIRST" when using dual clocks with EDK pcore.
A patch is available for 64-bit windows. See (Xilinx Answer 56214)
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 56214 | System Generator for DSP v14.5 - Patch Update for numerous known issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34859 | Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap | N/A | N/A |