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AR# 56390

Vivado Simulation : How do I compile libraries and perform simulation in Vivado using Synopsys VCS

Description

In Vivado Design Suite, the simulation libraries and models have changed from ISE.

How do I perform VCS simulation in Vivado?

Solution

Overview:

VCS provides for two methods of referencing Xilinx model libraries for Functional and Gate Level Simulation: Precompiled, and Dynamic.

Notes: 

The method of library reference in Vivado has changed from ISE. The changes of note are:
 
  • The UNISIM library now contains both functional and timing simulation models.
  • A parameter xil_timing now indicates whether UNISIM models are functional or timing.
  • A retarget library has been included for legacy device functional and timing simulation component models.
  • XilinxCoreLib is not required for Vivado simulation. It can be included if ISE based legacy IP is present.
  • The AXI BFM is license based, and requires a separate compilation step if licensed and used in the design.
  • The Vivado physical library directory path has changed from the ISE location (Logical Libraries are the same).

For more information, see Vivado Design Suite User Guide Logic Simulation (UG900).


Dynamic Library Compilation for Verilog Functional Simulation

Functional Simulation Command using VCS
    vcs -y $XILINX_VIVADO/data/verilog/src/unisims                            \
        -y $XILINX_VIVADO/data/verilog/src/unimacro                           \
        -y $XILINX_VIVADO/data/verilog/src/retarget                           \
        -y $XILINX_VIVADO/ids_lite/ISE/verilog/src/XilinxCoreLib              \    
        -f $XILINX_VIVADO/data/secureip/secureip_cell.list.f                  \
        -f $XILINX_VIVADO/data/secureip/axi_bfm/axi_bfm_cell.list.f           \
        +incdir+$XILINX_VIVADO/verilog/src +libext+.v                         \
        $XILINX_VIVADO/verilog/src/glbl.v                                     \
        +verilog2001ext+.vp -lca -Mupdate -R <testfixture>.v <design>.v
    
VCS Option Notes:    
-y                      : include subdirectories
-f                      : include file list
-R                      : Automatically updates simulation executable after compilation
+verilog2001ext+.vp     : States that SecureIP should be treated as verilog 2001 syntax
-lca                    : Enable SecureIP model decryption 
-Mupdate                : Enables incremental compilation
 
Library Notes:
unisims                 : Xilinx primitive functional models
unimacro                : Macros models for large scale primitives
retarget                : unisim/simprim retarget library for older architectures
XilinxCoreLib           : ISE legacy IP models
vcs_secureip_cell.list  : List of secure IP components for inclusion
axi_bfm_cell.list       : Optional Encrypted AXI BFM model (requires license)
 
Dynamic Library Compilation for Verilog Timing Simulation

Timing simulation is a three step process consisting of:
 
  • Generating the simulation netlist (timesim.v generation)
  • Annotating timing information to the netlist (SDF file generation)
  • Analyzing, elaborating, and simulating the timing netlist and SDF using VCS

Timing Netlist/SDF Generation in Vivado:

write_verilog -mode timesim -sdf_file <sdf_file>.sdf <sim_netlist>.v
write_sdf <sdf_file>.sdf


Timing Simulation Command in VCS
    
 vcs +compsdf -y $XILINX_VIVADO/data/verilog/src/unisims              \
     $XILINX_VIVADO/data/verilog/src/glbl.v                           \
     -f $XILINX_VIVADO/data/secureip/secureip_cell.list.f             \
     +libext+.v +transport_int_delays +pulse_int_e/0 +pulse_int_r/0   \
     -Mupdate -R <testfixture>.v <sim_netlist>.v

VCS Option Notes:    
    -y          : include library subdirectories
    +compsdf    : compile SDF file and back annotate timing info to design
    -Mupdate    : Enables incremental compilation
 
Library Notes:
 
    unisims     : Xilinx primitive functional/timing models

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58891 Xilinx Simulation Solution Center - Design Assistant - Third Party Simulators - Synopsys VCS​/VCS-MX N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
60154 2014.1 Install - XILINX_VIVADO and LD_LIBRARY_PATH environment variables are not set in settings64.bat/sh files N/A N/A
AR# 56390
Date Created 06/13/2013
Last Updated 04/15/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite