UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56429

2013.3 Vivado Logic Debug - Static nets connected to debug cores (ILA/VIO) in HDL are not preserved

Description

I am connecting static nets (signals assigned constant values) to an ILA/VIO core in the HDL code in Vivado 2013.3.

These nets are not preserved after Synthesis and a mark_debug attribute is not applied.

How can I resolve this?

Solution

This issue is not seen in the 2013.4 and 2014.1 releases. 

If you encounter this issue, the workaround is to manually apply the mark_debug attribute in HDL.

AR# 56429
Date Created 06/14/2013
Last Updated 09/04/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.3