We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56451

MIG 7 Series and Virtex-6 DDR3/DDR2 - UG586 and UG406 have incorrect signal descriptions for the native interface "cmd" signal


For both the Virtex-6 and 7 series FPGA MIG DDR3/DDR2 designs, the "cmd" signal is the Native Interface input that selects the command for the current request.

In the Virtex-6 and 7 series FPGA Memory Interface User Guides (UG406 and UG586), the codes for the "cmd" bus are incorrect; showing a read is signified by "000" and a write by "001".


This will be resolved in a later revision of these two documents.

Be sure to signify a read with "001" and a write with "000" when interfacing to the Native Interface. The tables for the app_cmd input to the User Interface are correct.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56451
Date Created 06/17/2013
Last Updated 07/26/2013
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series
  • MIG Virtex-6 and Spartan-6