Description

This Answer Records describes how to use CLKDLL in a Virtex design.

Solution

CLKDLL verilog example(This example uses CLK2X output): 

module useclk (Din, clk, Dout, locked); 

input Din, clk;  

output Dout, locked;  

reg Dout;  

wire clk_int,clk_bufg,a,b,c,d,e,f,gd;  

assign gd=1'b0;  

BUFG U0 (.I(clk_int), .O(clk_bufg));  

CLKDLL U1(.CLKIN(clk),.RST(gd),.CLKFB(clk_bufg),.CLK0(a),.CLK90(b),.CLK180(c),  

.CLK270(d),.CLKDV(e),.CLK2X(clk_int),.LOCKED(locked));  

always@(posedge clk_bufg)  

begin  

Dout<=Din;  

end  

endmodule

CLKDLL vhdl example (this example uses CLK2X output): 

library ieee; 

use ieee_std_logic_1164.all; 

entity useclk is 

port (Din, clk : in std_logic; 

Dout, locked : out std_logic); 

end useclk; 

architecture useclk_arch of useclk is 

component BUFG port (I: in std_logic; O: out std_logic); 

end component; 

component CLKDLL port ( 

CLKIN, CLKFB, RST : in std_logic; 

CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic); 

end component; 

signal clk_int, clk_bufg,a,b,c,d,e,gd : std_logic; 

begin 

gd<='0'; 

U0 : BUFG port map (I=>clk_int, O=>clk_bufg); 

U1 : CLKDLL port map( 

CLKIN=>clk, 

RST=>gd, 

CLKFB=>clk_bufg, 

CLK0=>a, 

CLK90=>b, 

CLK180=>c, 

CLK270=>d, 

CLKDV=>e, 

CLK2X=>clk_int, 

LOCKED=>locked); 

process (clk_bufg) 

begin 

if (clk_bufg'event and clk_bufg='1') then 

Dout<=Din; 

end if; 

end process; 

end useclk_arch;

CLKDLLs must be instantiated in the HDL code. There are no synthesis tools that currently can infer them. Resolutions 1 and 2 illustrate the easiest CLKDLL usage when BUFGDLL component is used. However, BUFGDLL allows users to access only CLK0 output pin. If any other CLKDLL output pins need to be used, CLKDLL component must be instantiated. Please see resolutions 3 and 4.  

BUFGDLL Verilog Example: 

module useclk (Din, clk, Dout);  

input Din, clk;  

output Dout;  

reg Dout; wire clk_int;  

BUFGDLL U0(.I(clk), .O(clk_int));  

always@(posedge clk_int)  

begin Dout<=Din;  

end endmodule

BUFGDLL VHDL example:  

library ieee;  

use ieee.std_logic_1164.all;  

entity useclk is  

port (Din, clk : in std_logic;  

Dout : out std_logic);  

end useclk;  

architecture useclk_arch of useclk is  

component BUFGDLL port (I : in std_logic; O : out std_logic);  

end component;  

signal clk_int : std_logic;  

begin  

U0 : BUFGDLL port map(I=>clk, O=>clk_int);  

process (clk_int)  

begin  

if (clk_int'event and clk_int='1') then  

Dout<=Din;  

end if;  

end process;  

end useclk_arch;