2013.2 Vivado Synthesis does not infer a shift register for a HDL design containing a clock enable in spite of setting the shreg_extract attribute to "yes," and instead flip-flops and LUTs are inferred.
Why does synthesis not infer shift register for this scenario? How to get around this issue?
Here is a sample Verilog code:
module top(clk, clken, SI, SO);
parameter WIDTH = 16;
input clk, clken, SI;
(* shreg_extract = "yes" *)reg [WIDTH-1:0] shreg;
always @(posedge clk)
shreg <= SI;
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
assign SO = shreg[WIDTH-1];
This issue has been fixed in 2013.3. The above code results in shift register correctly.
For the above Verilog code, 2013.2 Vivado Synthesis does not infer a shift register, in spite of setting the shreg_extract attribute to "yes". In the above code, the shift register is 16 bits wide. For the above scenario, Vivado synthesis does not infer a shift register and instead flip-flops and LUTs are inferred. Also, clken in the above code is passed to the input of the generated LUTs, which is used to emulate the CE behavior of the flip-flops, and the actual flip-flop CE is connected to '1'. Shift register is inferred for register data widths greater than or equal to 20, and also the clken in this case goes directly to the CE of the SRL and flip-flops. Shift register is not inferred for data widths less than 20. This behavior has been attributed to a change in the threshold limit, which the development team is aware of, and is in the process of finding an efficient solution. 2013.1 Vivado Synthesis does not show this behavior and does infer shift registers correctly for the above HDL code.
To work around this issue in 2013.2, the following Tcl parameter can be used,
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter enableControlSetsOpt false"
Using this Tcl command, 2013.2 Vivado Synthesis does infer a shift register for the above mentioned sample Verilog code.