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AR# 56533

2013.1 Vivado IP Flows - An error occurs when generating example design for a 7 series FPGA Transceiver


I have customized a 7 series FPGA Transceiver with the following configuration:

set_property -dict

When I right-click the xci and try to generate the example design, the following error occurs:

Generating IP 'gtwizard_0'...
Delivering 'Examples Synthesis' files for IP 'gtwizard_0'.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2013.1/data/ip/xilinx/gtwizard_v2_5/ttcl/init_family012.ttcl':
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-1710] Problem delivering 'Examples Synthesis' files for IP 'gtwizard_0'.
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate 'Examples Synthesis' output product for IP 'gtwizard_0': Failed to copy files.
[list CONFIG.gt_val_drp {true} CONFIG.gt_val_drp_clock {50} CONFIG.gt0_val {false} CONFIG.gt2_val {true} CONFIG.gt2_val_tx_refclk {REFCLK0_Q0} CONFIG.gt0_val_encoding {8B/10B} CONFIG.gt0_val_decoding {8B/10B} CONFIG.gt0_val_drp_clock {50} CONFIG.gt0_val_port_txchardispmode {true} CONFIG.gt0_val_port_txchardispval {true} CONFIG.gt0_val_port_rxchariscomma {true} CONFIG.gt0_val_txoutclk_source {true} CONFIG.gt0_val_rxbuf_en {true} CONFIG.gt0_val_rxusrclk {TXOUTCLK} CONFIG.gt0_val_port_txpcsreset {true} CONFIG.gt0_val_port_txbufstatus {true} CONFIG.gt0_val_port_txrate {true} CONFIG.gt0_val_port_rxpcsreset {true} CONFIG.gt0_val_port_rxbufstatus {true} CONFIG.gt0_val_port_rxbufreset {true} CONFIG.gt0_val_port_rxrate {true} CONFIG.gt0_val_port_txpmareset {true} CONFIG.gt0_val_port_txsysclksel {true} CONFIG.gt0_val_port_rxpmareset {true} CONFIG.gt0_val_port_rxsysclksel {true} CONFIG.gt0_val_port_rxcdrhold {true} CONFIG.gt0_val_port_rxpcommaalignen {true} CONFIG.gt0_val_port_rxmcommaalignen {true} CONFIG.gt0_val_port_rxslide {false} CONFIG.gt0_val_port_rxbyteisaligned {true} CONFIG.gt0_val_port_rxbyterealign {true} CONFIG.gt0_val_port_rxcommadet {true} CONFIG.gt0_val_txdiffctrl {true} CONFIG.gt0_val_txpostcursor {true} CONFIG.gt0_val_txprecursor {true} CONFIG.gt0_val_txmaincursor {true} CONFIG.gt0_val_rx_termination_voltage {AVTT} CONFIG.gt0_val_port_txpolarity {true} CONFIG.gt0_val_port_txinhibit {true} CONFIG.gt0_val_port_rxpolarity {true} CONFIG.gt0_val_port_pll0pd {true} CONFIG.gt0_val_port_pll1pd {true}] [get_ips gtwizard_0]


This issue is resolved in Vivado Design Suite 2013.2.
AR# 56533
Date Created 06/21/2013
Last Updated 12/20/2013
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.1
  • 7 Series FPGAs Transceivers Wizard
  • IO Interfaces