We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56609

2013.2 Vivado IPI, Zynq-7000 - How do I connect custom AXI HDL outside of IPI to a Zynq AXI interface?


I would like to connect my custom AXI master or slave to a Zynq AXI interface, but prefer to manage the HDL outside of IPI (IP integrator). How do I accomplish this?


The following example is used to add an AXI4-Lite custom IP to Zynq AXI_GP0 on a ZC702 board, using Vivado to manage the custom AXI HDL outside of an IPI block diagram.

Note: The resulting Vivado 2013.2 project is attached below. To use, run the "hello world" application in SDK workspace to demonstrate the access of the peripheral from an ARM CPU.

1. Create a Vivado project based on ZC702 board.
2. Click IP Integrator-> Create Block Design.
3. Add ZYNQ7 Processing System and AXI Interconnect IP. The AXI Interconnect is preferred due to the automatic services it provides: protocol conversion (AXI3->AXI4LITE in this case), register slices, FIFOs, and clock conversion.
4. Double-click the AXI Interconnect IP and configure the Number of Slave Interfaces and Number of Master Interfaces to 1. Click OK to save the change.
5. Connect the interconnection between the IPs similar to below:

6. Click Run Block Automation and select /Processing_system7_1 to make DDR and FIXED_IO interface external.

7. Right-click the M_AXI port and select Make External.

8. Right-click FCLK0 port and select Create Port.... Change the Port name to ACLK. The purpose of this is to provide the AXI CLK to the HDL outside of IPI since the clock and reset is not part of a bundled AXI interface. Perform the same operation to FCLK_RESET0_N and change the Port name to ARESETN.

9. Right-click the M00_AXI port and select External Interface Properties.

10. Click the General tab, choose "ACLK" as Clock Port. This is required to enable IPI to understand the clock frequency of the external interface. Otherwise, a Critical Warning similar to the following will occur:
[BD 41-968] AXI interface port /M00_AXI is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port.

11. Click the Properties tab, expand the CONFIG list, set the PROTOCOL to "AXI4LITE." While this is set on the external interface port, the AXI Interconnect will query this setting and automatically use a protocol_converter block to convert the AXI3 interface of M_AXI_GP0.

12. Assign the address for M00_AXI in Address Editor tab. Right-click it and select Auto Assign Address. This will be the address range for accesses that will be routed to the external AXI4LITE peripheral. Modify as desired.

13. Go back to Vivado source window and right-click your block design and select Generate Output Products... to save the project.

14. Note: There is a known issue in Vivado 2013.2. The AXI4Lite ports will not be updated in the external wrapper unless the BD (block diagram) is closed and reopened. For more information please refer to (Xilinx Answer 56584). If using a later version (2013.3 e.g.) please skip steps 14 and 15.Close the block design then double-click it to reopen it.

15. Right-click your block design and select Generate Output Products.... to regenerate the Output Products.
16. Right-click your block design, select Create HDL Wrapper.
17. Open the resulting file and notice the AXI external master signals that were exposed.

18. Add/Create custom IP code sources to Vivado project. Collections of example AXI cores are available in (Xilinx Answer 37425). The HDL files contained in these cores can be extracted to be used as a starting point.
19. Modify the top-level HDL to instantiate the custom AXI peripheral, and connect to the external connector signals on the IPI block instantiation.

20. Save the top-level HDL file and continue with design flow, such as generating a bitstream.

Note: To get more Vivado IP Integrator design information please go to (Xilinx Answer 56612) - Vivado IP Integrator Solution Center.


Associated Attachments

Name File Size File Type
zc702_ipi_ext_axilite_update.rar 6 MB RAR
AR# 56609
Date Created 06/27/2013
Last Updated 12/02/2013
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2013.2
  • AXI Interconnect
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit