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AR# 56611

2013.2 Vivado IP Integrator - "ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /mig_7series_1/S_AXI and /axi_interconnect/M_AXI"


In a simple Vivado IP Integrator system with a mig_7series, IP connects to an external AXI interface via a AXI Interconnect. However, during Generate Output Products I am seeing the error similar to below:

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /mig_7series_1/S_AXI(design_1_mig_7series_1_1_ui_clk) and /axi_interconnect_1/s00_couplers/auto_us_df/M_AXI(design_1_ACLK)

How can I fix this issue?


This error is indicating that the IP does not know the relationship between the AXI Interconnect S00 ACLK and the MIG's ui_clk. The ui_clk is the DDR clock /2 or /4 depending on the MIG configuration. If you use the ui_clk output to drive the other AXI clocks on the Interconnect, the design should validate successfully.

However, in this case the ACLK on the interconnect's external interface properties need to be updated to include the correct clock domain. To do this highlight the S00_ACLK, and in the AXI External Interface Properties:


The CLK_DOMAIN can be obtained by clicking on the ui_clk pin and veiwing the properties.

AR# 56611
Date 06/27/2013
Status Active
Type General Article
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.2
  • AXI Interconnect
  • MIG 7 Series