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AR# 56616

7 Series Integrated Block for PCI Express - Link Training Debug Guide

Description

This answer record provides a link training debug document for 7 Series Integrated Block for PCI Express in a downloadable PDF to enhance its usability. Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.

Solution

Please download the Debugging Guide for 7 Series Integrated PCI Express Block Link Training Issues which is attached in PDF format at the end of this answer record; file name is "Xilinx_Answer_56616_7_Series_PCIe_Link_Training_Debug_Guide.pdf".

This document describes techniques to debug link training issues with 7 Series Integrated PCI Express Block.  A  complete  list  of  signals  to  capture in ChipScope Pro/Vivado ILA when debugging link training issues has been provided. Screen captures of the signal waveforms illustrate how to analyze those signals and establish theories on potential reasons causing the problem. One of the main reasons behind running into the link training issue is due to the Signal Integrity (SI) issue on the board. A general guideline of things to check has been provided to debug probable issues due to SI.

The link training issue does not entirely depend on the PCIe Core. It is equally a function of the board and how the system is connected up. Therefore, it is important to make sure that all the factors affecting the signal integrity on the board should be thoroughly checked (e.g. reference clock quality, voltage signal level etc.). There are few transceiver parameters that a user could tune to suit their system. This has been discussed in this document.

Revision History
06/10/2013 - Initial Release

Attachments

Associated Attachments

AR# 56616
Date Created 06/27/2013
Last Updated 08/12/2013
Status Active
Type General Article
IP
  • 7 Series Integrated Block for PCI Express (PCIe)