While mapping a design in Vivado Design Suite 2013.2, the tool stops during synthesis with a fatal error that is shown below.
No further diagnostics are given that indicates what the problem is.
A number of Xilinx IPs have been used in the design for which we have license keys available on our license servers, and we also have a valid software floating licenses for our tools.
Why is this error being received?
INFO: [Synth 8-638] synthesizing module 'intr_block' [<project_directory>/eth_ip_2013.2/ten_gig_eth_mac_v12_0_0/ten_gig_eth_mac_v12_0/management/intr_block.vhd:145]
INFO: [Synth 8-256] done synthesizing module 'intr_block' (437#645) [<project_directory>/eth_ip_2013.2/ten_gig_eth_mac_v12_0_0/ten_gig_eth_mac_v12_0/management/intr_block.vhd:145]
INFO: [Synth 8-256] done synthesizing module 'ten_gig_eth_mac_v12_0_management' (438#645) [<project_directory>/eth_ip_2013.2/ten_gig_eth_mac_v12_0_0/ten_gig_eth_mac_v12_0/management/management.vhd:267]
Fatal Error. License Check failed for secure IP. Exiting Synthesis.
License Check diagnostics :
finished Rtl Elaboration : Time (s): cpu = 00:35:52 ; elapsed = 00:36:36 . Memory (MB): peak = 1833.906 ; gain = 1695.434
invoked from within
set ::env(BUILTIN_SYNTH) true
set rt::cmdEcho 0
3162 Infos, 1104 Warnings, 1 Critical Warnings and 0 Errors encountered.
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
The Vivado licensing scheme does not look for an IP core license feature on another server during Synthesis relative to where the Synthesis feature is found.
For this reason, the IP core licenses are not being found and the above error occurs.
In the meantime, to work around this issue, do one of the following:
For additional information, see (Xilinx Answer 52062).
This issue has been fixed in Vivado 2014.1.