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AR# 5662

Virtex JTAG - How to configure a Virtex device via JTAG with debugging options


keywords: Virtex, JTAG, TAP, configure, configuration, program, programming

urgency: hot

general description:

A Virtex chip can be configured via its dedicated JTAG pins.



There is a software requirement for configuring a single Virtex device via JTAG.
At a minimum, you must use A1.5i/F1.5i or better software when creating a
Virtex design that will be loaded via JTAG.

(1) Create a .bit file which uses the following option in bitgen.

bitgen -g startupclk:jtagclk designName.ncd
Where designName is the name of the routed ncd file.

If you do not do this the Virtex device will accept the bitstream, DONE
will be high and /INIT will be high, but the device will not respond to
stimulus. This option tells the Virtex device to use the JTAG clocks on the TCK
pin to finish the configuration process.

If you do not wish to use the TCK to clock the startup sequence then
you must use the STARTUP_VIRTEX symbol to attach a specific internal
clock net to be used for the startup sequence. Bitgen must then be
instructed to use the userclk for startup with the option -g:userclk

Failure to do either of these options will result in an incomplete device

(2) After creating a bitstream as per step 1, prepare the Virtex device for
JTAG configuration. If you are using the JTAG Programmer software,
then do not read any further. If you are using a JTAG tester or writing your
own software, the following applys:

An individual Virtex device can be configured via JTAG in two different ways.

In the first method, an already configured Virtex device is re-configured
via JTAG by toggling the TAP and entering the CFG_IN instruction. In the
second method, an individual Virtex device is configured after
power-up via JTAG exclusively.

If you are configuring a Virtex device via JTAG only, then it is
reccomended to set the mode pins of the Virtex device to 101
(M2=1,M1=0,M0=1 NOPULLUPS) or 001 (M2=0,M1=0,M0=1 PULLUPS).
If you do not set the mode pins to 101 or 001 before power-up, you risk
accidental configuration in another mode.

(3) After physically preparing the individual Virtex device, and creating the
bitstream with the correct bitgen options, follow these instructions to load the bitstream.

(a) On power-up, place a '1' on TMS and clock TCK five times. This takes the
TAP through the Test-Logic-Reset (TLR) state.

(b) Move to the Shift-IR state.

(c) In the Shift-IR state, load the CFG_IN instruction.

(d) Go to the Shift-DR state and shift in the Virtex bitstream. When the entire
bitstream has been shifted in, leave the Shift-DR state and go to the
Test-Logic-Reset state.

(e) From the Test-Logic-Reset state, go to Shift-IR and load in the JSTART
instruction. After loading the JSTART instruction, go to the Shift-DR
state and apply at a minimum 10 clocks to TCK.

(g) After applying the clocks to TCK, return to Test-Logic-Reset.

The device will now be functional.


Troubleshooting the JTAG Configuration of an Individual Virtex Device

Note that the TAP is always active on Virtex devices and can be used
for troubleshooting. In JTAG configuration mode, DONE
functions exactly as it does in non-JTAG configuration mode. While in
JTAG configuration mode with Virtex, the DONE pin can be monitored
to see if the bitstream has been successfully loaded into the device. If
DONE is low three things are possible: the entire bitstream hasn't been
sent, the entire bitstream has been sent but the startup sequence has
not finished, or an error has happened. If DONE goes high, this means
that the Virtex device has received the entire bitstream and that the
bitstream was not corrupted.

If DONE has not gone high , the bitstream has been created with the
-g option for jtagclk, and the JSTART instruction has been executed,
it is possible that an error in the bitstream was detected. In non-JTAG
configuration of a Virtex device, this sort of failure is revealed via the
/INIT pin. In Virtex JTAG configuration, the external /INIT pins not used
for reporting status. It is possible to view the internal /INIT signal. After
finishing a Virtex JTAG configuration where the DONE pin stays low, do the
following to see if an error in the bitstream was detected:

(a) Move the TAP to the test-logic-reset state.
(b) Load the CFG_IN instruction.
(c) go to the Shift-DR state and shift in this 64-bit pattern:

2 8 0 0 E 0 0 1 0 0 0 0 0 0 0 0
0010 1000 0000 0000 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000
Shift in data starting from this bit.

(d) Load the CFG_OUT instruction.
(e) go to Shift-DR and clock TCK 32 times while reading TDO.

The data is the contents of the STATUS register. The last bit out will be
a 1 if there was a CRC error. After a successful configuration the 32 bits
would normally be:

0000 0000 0000 0000 0 1 1 111 1 1 0 1 0 1111 0

The rightmost bit is the last one shifted out. If the returned values
deviates from the above there may be a problem with your configuration.
For a complete description of the bits in the STATUS register please
see Xilinx Application Note (Xilinx XAPP151) "Virtex Configuration Architecture
Advanced Users' Guide"
AR# 5662
Date Created 02/13/1999
Last Updated 02/10/2007
Status Archive
Type General Article