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  3. AR# 56623: LogiCORE IP AXI Video Direct Memory Access v6.0 - S2MM_TREADY stays deasserted in my IPI design

AR# 56623

LogiCORE IP AXI Video Direct Memory Access v6.0 - S2MM_TREADY stays deasserted in my IPI design

Description

I have designed a video system that makes use of the AXI VDMA v6.0 (Rev. 1) core in 2013.2 IPI. I am observing that the MM2S channel is working fine, but the S2MM channel is throttling back by deasserting tready indefinitely after a few beats. What is wrong? How do I debug this?

Solution

Most Xilinx Video IP currently do not drive the output tkeep signal (i.e. Video Scaler, Video In to AXI4 Stream, etc). Further, the default tieoff for s_axis_s2mm_tkeep on the AXI VDMA in IPI is currently 0. When tkeep is not driven by any upstream IP, this results in the AXI VDMA interpreting all bytes as null bytes and thus it cannot transfer data to memory. tready will deassert indefinitely after internal buffers are filled.

The solution is to drive the s_axis_s2mm_tkeep signal appropriately.

This was first discovered in the AXI VDMA v6.0 (Rev. 1) in 2013.2 and it will be addressed in a future release of the tools.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54448 LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56623
Date 06/28/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
IP
  • AXI Video Direct Memory Access
  • AXI Video DMA
  • AXI Video DMA
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