UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56625

LogiCORE Tri-Mode Ethernet MAC v7.0, Vivado, 7 Series - Updates needed for xdc file and Verilog bus2ip_addr bus if configured to use Configuration Vector

Description

In Vivado Design Suite 2013.2, if using the Tri-Mode Ethernet MAC v7.0 core and it is configured to use the Configuration Vector, there is syntax that needs to be updated for the Verilog version of the core. Additional false path constraints are also needed to avoid the possibility of timing errors on asynchronous paths.

Solution

1) In the Verilog core block level, the instantiation of the core has a syntax error.

The line:

      .bus2ip_addr  {12{1'b0}},

Should be changed to:

      .bus2ip_addr  ({12{1'b0}}),

2) In the core xdc file, you will need to add:

set_false_path -through [get_ports {rx_configuration_vector[*]}]
set_false_path -through [get_ports {tx_configuration_vector[*]}]


This has been addressed in the v7.0 (Rev1) update (Xilinx Answer 57446) and will also be addressed in the v8.0 core scheduled to be released in Vivado Design Suite 2013.3.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57446 Tri Mode Ethernet MAC v7.0 (Rev1) - Downloadable Rev1 patch update N/A N/A
AR# 56625
Date Created 06/27/2013
Last Updated 10/03/2013
Status Active
Type General Article
IP
  • Tri-Mode Ethernet MAC