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AR# 56626

Vivado 2013.2 - A critical warning occurs "[Constraints 18-639]" that suggests I have set an IOB property to FALSE even though it is set to TRUE


In my Vivado design, the output of register data_reg[2][0] is connected to port dout[0].

I set IOB as true for port dout[0] and loc the register data_reg[2][0] at the same time.

set_property IOB TRUE [get_ports {dout[0]}]
set_property LOC OLOGIC_X0Y2 [get_cells {data_reg[2][0]}]

When opening the synthesized design, the following critical warning is reported:

[Constraints 18-639] Setting IOB property to FALSE on port dout[0] conflicts with the current LOC constraint (OLOGIC_X0Y2) on its connected flop dout[0]. The LOC constraint will be removed.

However, ports dout[*] has IOB property of TRUE.

%get_property IOB [get_ports dout[0]]


This issue has been fixed in 2013.3 version of the tools.

To work around this issue, modify the xdc as follows.

set_property IOB TRUE [get_cells {data_reg[2][0]}]
set_property LOC OLOGIC_X0Y2 [get_cells {data_reg[2][0]}]
AR# 56626
Date Created 06/28/2013
Last Updated 12/17/2013
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2