UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56632

14.6 SDK - Cannot configure Programmable Logic from boot image if DDR has ECC enabled

Description

I cannot configure Programmable Logic from the boot image if DDR has ECC enabled.

How can this be addressed?

Solution

To address this issue, two files need to be modified, (ps7_init.tcl, and ps7_init.c ) found in the hw_platform in SDK.

Open the ps7_init.tcl, and modify from:

set PS7_XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x0FFFFFFF

to:

set PS7_XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

 

Open the ps7_init.c, and modify lines:

#define PS7_MASK_POLL_TIME 100000
#define PS7_XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

to:

#define PS7_MASK_POLL_TIME 1000000000
#define PS7_XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

After these changes have been made, rebuild the FSBL by cleaning all project files (Project -> Clean).

AR# 56632
Date Created 06/28/2013
Last Updated 07/01/2013
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.6
  • Vivado Design Suite - 2013.2