We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56645

2013.2 IP Integrator - Cannot successfully connect both M_GP ports from Zynq-7000 to single AXI_Interconnect


In 2013.2 IP Integrator, I cannot bring both M_GP ports to a single AXI_Interconnect.

If I attempt to make both connections, I receive the following error when I attach memory-mapped slaves to the second address-range of the PL (0x8000_0000 to 0xBFFF_FFFF):

"ERROR: [BD 41-70] Exec TCL: <0x80001000[ 4K ]> is not within the range limit <0x40000000[ 1G ]> for this segment"

"ERROR: [Common 17-39] 'set_property' failed due to earlier errors."


To work around this issue, instantiate two AXI_Interconnects; one for each PL address range (0x4000_0000 to 0x7FFF_FFFF) and (0x8000_0000 to 0xBFFF_FFFF).
AR# 56645
Date Created 07/01/2013
Last Updated 07/01/2013
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2013.2
  • AXI Interconnect