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AR# 56647

AXI Memory Mapped to PCI Express v2.1 - Core Constraints are not Generated

Description

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 54646).

When generating the AXI Memory Mapped to PCI Express core v2.1 and targeting a Xilinx Development Board, the core constraint file (XDC) is not generated. The core constraint file should include timing constraints for the core.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution

There is an issue with the Tcl script that is used by Vivado tools to generate the AXI Memory Mapped to PCI Express core constraint file. The issue will be fixed in future release of the core.

For a current workaround:

1) Navigate to the <Xilinx install directory>/Vivado/2013.2/data/ip/xilinx/axi_pcie_v2_1/ttcl
2) Find these files and edit the content as shown below:
     xilinx_pcie_2_1_7x_x#y#_xdc (There are multiple files for each different PCIe hard block location, edit all of them).
3) Find this line and remove it from the Tcl file (should be around line #3):
     <: if {$xlnx_ref_board_ucf} ttcl_return :>
4) Regenerate the core in Vivado. The XDC file should now show up within the <core_name>.xci file hierarchy and contain the core specific timing constraints.

Revision History:
8/26/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54646 AXI Bridge for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56647
Date Created 07/01/2013
Last Updated 08/27/2013
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)