We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56710

ISE MAP - ERROR:PhysDesignRules:1487 - The placed IODELAYE1 component


The following error was seen during MAP for an incorrect IODELAY configuration involving VAR_LOADABLE mode:


ERROR:PhysDesignRules:1487 - The placed IODELAYE1 component
   i_data_interface_pro/channel_B_data_capture/io[0].iodelaye1_data has the C pin connected to the signal
   i_data_interface_pro/channel_B_data_capture/GLOBAL_LOGIC0 while the adjacent site has the placed ISERDESE1 component
   i_data_interface_pro/channel_B_data_capture/io[0].ISERDESE1_inst with the CLKDIV pin connected to the signal
   i_data_interface_pro/channel_B_data_capture/dclk_div2. These two pins share the routing resource and the use of
   separate signals creates a routing resource conflict. Only one signal can be used for these two pins.


Please refer to the Virtex-6 FPGA SelectIO Resources User Guide (UG361), under the section "IODELAYE1 Ports".

"Clock Input - C
All control inputs to IODELAYE1 primitive (RST, CE, and INC) are synchronous to the clock input (C).
A clock must be connected to this port when IODELAYE1 is configured in VARIABLE or VAR_LOADABLE mode.
C can be locally inverted, and must be supplied by a global or regional clock buffer.
This clock should be connected to the same clock in the SelectIO logic resources (when using ISERDES and OSERDES, C is connected to CLKDIV)."


The C pin should be connected to the same clock as the ISERDES's CLKDIV.

AR# 56710
Date 03/18/2015
Status Active
Type General Article
  • Virtex-6
Page Bookmarked