UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56740

2013.2 Vivado IP Integrator- Zynq GP0 and GP1 ports should allow for 2GB address space access

Description

According to Zynq TRM the address ranges for M_AX_GP0 and M_AXI_GP1 are 0x4000_0000 to 0x7FFF_FFFF and 0x8000_0000 to 0xBFFF_FFFF respectively.

This means that each has access to 1 GB of address space.
 
To achieve this using 2013.2 Vivado IPI, I enable both of the master GP ports, and I try to access an IP present in the PL side using a 2:1 (2 Master GP ports and 1 Slave - IP) configuration of the AXI interconnect.

however, the address editor GUI only shows the 0x4000_0000 to 0x7FFF_FFFF (1GB) address that corresponds to M_AXI_GP0.

I do not see the 0x8000_0000 to 0xBFFF_FFFF address space corresponding to M_AXI_GP1.

Is this expected behavior?

Solution

This issue has been fixed in Vivado Design Suite 2013.3 and later.

AR# 56740
Date Created 07/12/2013
Last Updated 02/24/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.2