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AR# 56750

2013.2 Vivado - Redundant line added in the entity declaration when creating VHDL source in Add sources -> Create File


When I create a VHDL file using the Add Sources -> Add or create design sources -> Create File in 2013.2 Vivado IDE, the created VHDL file has the entity declaration specified twice as shown below:

entity test is
entity test is
    Port ( f : in STD_LOGIC);
end test;

This results in a critical warning similar to the following:

[HDL 9-806] Syntax error near "entity". ["../../project_3/project_3.srcs/sources_1/new/test.vhd":35]


This issue occurs in the Vivado 2013.2 tool.

To work around the problem, you should manually remove the redundant line from the file.

This issue has been fixed in Vivado Design Suite 2013.3.

AR# 56750
Date 10/30/2013
Status Archive
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.2
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