UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56775

7 Series - Why do I see additional power consumption when I attempt Boundary Scan testing?

Description

When carrying out Boundary Scan testing, I observe that there is additional power drawn by the device when the SAMPLE instruction is loaded.

Why is this extra current drawn by the FPGA?

Solution

To carry out Boundary Scan testing, SelectIO pins and GT pins need to be set up.

  • For SelectIO pins, the SAMPLE instruction will force the input buffer to LVCMOS. If the input level is floating between the rails for LVCMOS (without a pull-up), then additional current draw can be seen.
  • For GT pins, the SAMPLE instruction will turn on the band-gap and pad driver to get ready for AC-JTAG (IEEE 1149.6) operation. This will increase power consumption for an unconfigured device as the GT will be in power down mode.

The additional current consumed will not exceed the current consumed in normal user operation. The current consumed is not documented as it will not be higher than normal operation and is not a risk for the device.

In UltraScale, the GT Quad power can be controlled via specific boundary-scan cells that can be found via the diff of "safe values" between the PRODUCTION and ES2 BSDL files.
Modifying these bits between 0 (ON) or 1 (OFF) results in the boundary-scan test vectors that keep the GT enabled/disabled. The consequence of disabling it is that the GTs are disabled and boundary-tests on the GT pins would not work.

AR# 56775
Date Created 07/16/2013
Last Updated 12/02/2016
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000
  • Virtex-7Q
  • Kintex-7Q
  • Artix-7Q
  • Kintex UltraScale
  • Virtex UltraScale
  • Less