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AR# 56777

LogiCORE IP DisplayPort v4.0 - GTH Common Block Refclk is not Connected Causing DRC Error


When implementing a DisplayPort TX core (2.7G line rate, all default settings), the GTH common block have the GTREFCLK0 pin left floating. 

This causes the following DRC error in Vivado:

[Drc 23-20] Rule violation (REQP-45) must_use_ref_clock - displayport_0_tx_inst/inst/dport_tx_phy_inst/gth_wrapper_inst/gthe2_common_0_i: An input reference clock pin must be used.


This issue will be fixed in the DisplayPort v4.1 core.

In the meantime, to work around the problem, follow the steps below:

  1. Navigate to <Project_directory>\.srcs\sources_1\ip\displayport_0\displayport_0\src   and then open <core_name>_gth_7_series_wrapper_4.v
  2. Find this line in the GTHE2_common instantiation:
      .GTREFCLK0                      (GT0_GTREFCLK0_COMMON_IN),
    Change it to:
      .GTREFCLK0                      (GT0_GTREFCLK0_IN),
  3. Reset your synthesis and implementation runs and the issue should now be resolved.

For a detailed list of Vivado LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 54522)

Revision History
7/17/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54522 LogiCORE IP DisplayPort - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56777
Date Created 07/16/2013
Last Updated 08/27/2014
Status Active
Type General Article
  • DisplayPort