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AR# 5682

FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design

Description

Keywords: OBUF, OBUFE, OBUFT, 9500

Urgency: Standard

General Description: After instantiating an OBUFE in an HDL design, FPGA Express
will also place an OBUF after the OBUFE and cause multiple drivers errors during
the Translate phase of implementation (NGDBUILD).

Solution

1

Infer the functionality of the OBUFE. For example:

VHDL:
DOUT <= DATA when ENABLE='1' else 'Z';

Verilog:
assign DOUT = ENABLE ? DATA : 1'bZ;

2

Instantiate an OBUFT and invert the signal that is used for the T pin.
AR# 5682
Date Created 02/16/1999
Last Updated 08/27/2001
Status Archive
Type General Article