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AR# 56844

Spartan-6 HSSIO - Is the duty cycle of the GTPCLKOUT0 (TXOUTCLK0) clock 40% High, 60% Low, or 60% High, 40% Low, when INTDATAWIDTH is High?

Description

Is the duty cycle of the GTPCLKOUT0 (TXOUTCLK0) clock 40% High, 60% Low, or 60% High, 40% Low, when INTDATAWIDTH is High?

Simulation results show that the duty cycle of the GTPCLKOUT0(TXOUTCLK0) clock is 40% High, 60% Low.

However, UG386, Spartan-6 FPGA GTP Transceivers User Guide, mentions 60/40.

Solution

The simulation results are correct.

It has also been confirmed on hardware that results match those of simulation, duty cycle of GTPCLKOUT0 (TXOUTCLK0)clock is 40% High, 60% Low.  This will be updated in a future release of the User's Guide.

AR# 56844
Date Created 07/23/2013
Last Updated 08/02/2013
Status Active
Type General Article
Devices
  • Spartan-6