Figure 1-56 from UG406 seems to imply that a single clock cycle of down time is required between each data word loaded on the user interface.
In BC4 configuration, the MIG controller still sends an 8-bit burst, but the last 4 bits are ignored by the SDRAM. The timing diagram above mimics loading the write data fifo in BL8 fashion, but ignores the second word. Is it possible to load BC4 words in a truly continuous, back-to-back fashion as shown in the BL4 example below?
Yes, it is possible to load data back-to-back in BC4 configuration; however, the write data FIFO will fill up twice as fast when loaded in this manner. Because data will be loaded twice as fast as the controller can write the data to memory, app_wdf_rdy will assert much sooner than for BL8. Figure 1-65 is shown with the gaps because this is the ideal way to load the write data FIFO at the correct pace in order to keep app_wdf_rdy High. If loading a BC4 MIG core with back-to-back writes, users need to make sure their logic throttles on app_wdf_rdy.