UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56861

Vivado Synthesis - ERROR: [Synth 8-1032] xxx is not declared in yyy

Description

If vhdl entity is instantiated by library reference (without explicit component declaration) and the library name is equal to an entity name that exists in this library, the following error message can occur in vivado synthesis:

Error: [Synth 8-1032] user_logic is not declared in dma_sm.

 

Example dma_sm.vhd:

library dma_sm;
use dma_sm.user_logic;
...

entity dma_sm is

...

USER_LOGIC_I : entity dma_sm.user_logic

 

 

Solution

To work around this issue, rename either the library or the entity so that the library name is not the same as any entity name in it.
AR# 56861
Date Created 07/24/2013
Last Updated 01/21/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite