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AR# 56864

7 Series GTX wizard sets GTX QPLL port BGRCALOVRD[4:0] to 5'b00000 but (UG476) states that it should be 5'b11111


(UG476) (v1.9.1) indicates that the GTX QPLL port BGRCALOVRD[4:0] should be set to 5'b11111 (see page 56). 

However, v2.5 and v2.6 of the GTX Wizard sets this to 5'b00000.   

Which is correct?

If I build a GTX in CORE Generator using the QPLL for Tx and Rx, I see in the generated file gtwizard_v2_6.vhd that the wizard adds in the following line in the gtxe2_common instance:

BGRCALOVRD                      =>      "00000",


You should follow the information in (UG476).

This should be set to 5'b11111.

This will be fixed in the 7 Series FPGAs Transceivers Wizard v3.1 in Vivado 2013.4.
AR# 56864
Date 06/10/2015
Status Active
Type General Article
  • Zynq-7000
  • 7 Series FPGAs Transceivers Wizard
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