UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56888

xapp585 - Incorrect behavior when Vivado synthesis used

Description

The xapp585 design might behave unexpectedly due to inference of incorrect FSM logic for the read_addra in the gearbox_4_to_7.v logic when Vivado synthesis tool 2013.1 or 2013.2 is used.

The following warning is issued by the tools.in 2013.1:

INFO: [Synth 8-2943] unable to generate logic for unpartitioned construct node

A post synthesis simulation can be used to check and verify correct behavior or if synthesis has changed any logic.

Solution

To work around this issue, place the KEEP attribute on "read_addra" for which FSM is inferred.

Before modification:  reg [3:0]   read_addra ;
After modification:  (* keep = "true" *) reg [3:0]   read_addra ;

For VHDL add the following lines:

attribute keep : string;
attribute keep of read_addra : signal is "true";

AR# 56888
Date Created 07/26/2013
Last Updated 07/29/2013
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2