UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56944

XAPP1081 Limitations

Description

This Article covers limitations in XAPP1081.

Solution

XAPP1081, QuickBoot Method for FPGA Design Remote Update, is delivered with verified reference designs for:

          SPI x1 from Micron N25Q, uniform boot, 128 Mb (or smaller)

-          BPI x16 asynchronous read mode from Micron P30

 

XAPP1081 is compatible with the following configuration options:

-          For SPI configuration mode with the Micron N25Q, uniform boot, 128 Mb (or smaller) flash:
 

o   SPI x1, x2, x4 buswidth (BitGen -g SPI_buswidth option)

o   SPI falling clock edge MISO data capture (BitGen -g SPI_Fall_Edge option)

o   External master CCLK (BitGen -g ExtMasterCclk_en option)

o   Encrypted bitstreams (BitGen -g Encrypt option)

-          For BPI configuration mode with the Micron P30 flash:
 

o   BPI page mode reads (BitGen -g BPI_page_size and -g BPI_1st_read_cycle options)

o   External master CCLK (BitGen -g ExtMasterCclk_en option)

o   Encrypted bitstreams (BitGen -g Encrypt option)

AR# 56944
Date Created 07/31/2013
Last Updated 03/10/2015
Status Active
Type General Article
Tools
  • ISE Design Suite
  • Vivado Design Suite