UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57004

FIR Compiler v7.1 - Post-synthesis and post-implementation netlists issue block RAM memory collision errors during simulation

Description

During simulation of the FIR Compiler, post-synthesis and post-implementation netlists memory collision errors are generated.

Solution

This is a known issue for some configurations of the FIR compiler IP when Block Memory is used by the core.

Post synthesis and implementation simulations might report block RAM memory collision errors. 

These errors are issued by the block RAM primitive when a write occurs and the read and write addresses match. 

However, a read or write event is qualified by read enable or write enable respectively. 

In operation, read and write events never occur to the same address at the same time so functionality is not affected by these apparent collisions.

The simulator break severity might have to be changed from ERROR to FAILURE to enable the simulation to continue beyond the memory collisions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54502 IP Release Notes and Known Issues for LogiCORE IP FIR Compiler core for Vivado 2013.1 and newer tools N/A N/A
AR# 57004
Date Created 08/06/2013
Last Updated 08/19/2014
Status Active
Type General Article
IP
  • FIR Compiler