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AR# 57046

2014.4 Vivado IP Integrator - AXI ports from Vivado CPRI do not match IP Integrator AXI external ports


If I make the AXI signals external in the IP Integrator block design, the resulting AXI signals do not match the CPRI IP AXI interface signals.

For example:

CPRI_MST_M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );  //From IPI
s_axi_arready : OUT STD_LOGIC;                            //From CPRI IP

This causes potential synthesis issues.


To address this issue, please consider one of the following work-arounds:

  • Set the Target Language to Verilog in the Project Settings, instead of VHDL.
    • To do this, click Project Manager -> Project Settings and change the Target Language to Verilog.
  • If you want to use VHDL:
    • You must perform bit slicing in the external HDL code.
    • Ensure that there is a coupler present, for example by turning on a register slice.
AR# 57046
Date 01/26/2015
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • More
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
  • Less
  • CPRI
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