A Planahead project is created with an XPS project added as a submodule that includes the AXI_BRAM_CTRL IP.
This is then exported to SDK with the "Include Bitstream" option.
However, the FPGA cannot now be programmed from SDK.
How can this issue be resolved?
This issue only arises when the "Include Bitstream" option is ticked in the "Export Hardware for SDK" screen in PlanAhead.
To work around this, generate the bitstream but do not select the "Include Bitstream" box in the "Export Hardware for SDK" screen in PlanAhead.
To Program the FPGA from SDK, Navigate to the .BIT and .BMM files from the impl_1 folder in the .runs directory in the PlanAhead Project directory as shown below: